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| cy14b101ka cy14b101ma 1-mbit (128 k 8/64 k 16) nvsram with real time clock cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-42880 rev. *k revised august 14, 2012 1-mbit (128 k 8/64 k 16) nvsram with real time clock features 1-mbit nonvolatile static random access memory (nvsram) ? 25 ns and 45 ns access times ? internally organized as 128 k 8 (cy14b101ka) or 64 k 16 (cy14b101ma) ? hands off automatic store on power-down with only a small capacitor ? store to quantumtrap nonvolatile elements is initiated by software, hardware, or autostore on power-down ? recall to sram initiated on power-up or by software high reliability ? infinite read, writ e, and recall cycles ? 1 million store cycles to quantumtrap ? 20 year data retention real time clock (rtc) ? full featured real time clock ? watchdog timer ? clock alarm with programmable interrupts ? capacitor or battery backup for rtc ? backup current of 0.35 a (typ) industry standard configurations ? single 3 v +20%, ?10% operation ? industrial temperature packages ? 44-/54-pin thin small outline package (tsop) type ii ? 48-pin shrink small outline package (ssop) pb-free and restriction of hazardous substances (rohs) compliant functional description the cypress cy14b101ka/cy14b101ma combines a 1-mbit nvsram with a full featured real time clock in a monolithic integrated circuit. the embedded nonvolatile elements incorporate quantumtrap tech nology producing the world?s most reliable nonvolatile memory. the sram is read and written an infinite number of times, while independent nonvolatile data resides in the nonvolatile elements. the real time clock function provides an accurate clock with leap year tracking and a programmable, high accuracy oscillator. the alarm function is programmable for periodic minutes, hours, days, or months alarms. there is also a programmable watchdog timer for process control. static ram array 1024 x 1024 r o w d e c o d e r column i/o column dec i n p u t b u f f e r s power control store/recall control quatrum trap 1024 x 1024 store recall v cc v ca p hsb a 0 a 1 a 2 a 3 a 4 a 10 a 11 software detect a 14 - a 2 oe ce we bhe ble a 5 a 6 a 7 a 8 a 9 a 12 a 13 a 14 a 15 a 16 dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 dq 8 dq 9 dq 10 dq 11 dq 12 dq 13 dq 14 dq 15 rtc mux a 16 - a 0 x out x in int v rtcbat v rtccap logic block diagram [1, 2, 3] notes 1. address a 0 ?a 16 for 8 configuration and address a 0 ?a 15 for 16 configuration. 2. data dq 0 ?dq 7 for 8 configuration and data dq 0 ?dq 15 for 16 configuration. 3. bhe and ble are applicable for 16 configuration only.
cy14b101ka cy14b101ma document number: 001-42880 rev. *k page 2 of 34 contents pinouts .............................................................................. 3 pin definitions .................................................................. 4 device operation .............................................................. 5 sram read ................................................................ 5 sram write ................................................................. 5 autostore operation .................................................... 5 hardware store (hsb) operation ............................ 5 hardware recall (power-up) .................................. 6 software store ......................................................... 6 software recall ....................................................... 6 preventing autostore .................................................. 7 data protection ............................................................ 8 noise considerations .................................................. 8 real time clock operation .............................................. 8 nvtime operation ....................................................... 8 clock operations ......................................................... 8 reading the clock ....................................................... 8 setting the clock ......................................................... 8 backup power ............................................................. 8 stopping and starting the osc illator ........... ........... ...... 9 calibrating the clock ................................................... 9 alarm ........................................................................... 9 watchdog timer ....... .............. .............. .............. ......... 9 power monitor ........................................................... 10 interrupts ................................................................... 10 flags register ........................................................... 11 maximum ratings ........................................................... 16 operating range ............................................................. 16 dc electrical characteristics ........................................ 16 data retention and endurance ..................................... 17 capacitance .................................................................... 17 thermal resistance ........................................................ 17 ac test loads ................................................................ 18 ac test conditions ........................................................ 18 rtc characteristics ....................................................... 18 ac switching characteristics ....................................... 19 sram read cycle .................................................... 19 sram write cycle ..................................................... 19 switching waveforms .................................................... 19 autostore/power-up recall ....................................... 22 switching waveforms .................................................... 22 software controlled store/recall cycle ................ 23 switching waveforms .................................................... 23 hardware store cycle ................................................. 24 switching waveforms .................................................... 24 truth table for sram operations ................................ 25 ordering information ...................................................... 26 package diagrams .......................................................... 27 acronyms ........................................................................ 30 document conventions ................................................. 30 units of measure ....................................................... 30 document history page ................................................. 31 sales, solutions, and legal information ...................... 34 worldwide sales and design s upport ......... .............. 34 products .................................................................... 34 psoc solutions ......................................................... 34 cy14b101ka cy14b101ma document number: 001-42880 rev. *k page 3 of 34 pinouts figure 1. pin diagram ? 44-pin, 54-pin tsop ii, and 48-pin ssop nc a 8 xin xout v ss dq 6 dq5 dq4 v cc a 13 dq 3 a 12 dq 2 dq 1 dq 0 oe a 9 ce nc a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 11 a 7 a 14 a 15 a 16 nc nc nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 44-pin tsop ii a 10 v rtcbat we dq 7 hsb int v ss v cc v cap v rtccap ( 8) nc dq 7 dq 6 dq 5 dq 4 v cc dq 3 dq 2 dq 1 dq 0 nc a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 v cap we a 8 a 10 a 11 a 12 a 13 a 14 a 15 nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 54- pin tsop ii oe ce v cc int v ss nc a 9 nc nc 54 53 52 51 49 50 hsb bhe ble dq 15 dq 14 dq 13 dq 12 v ss dq 11 dq 10 dq 9 dq 8 ( 16) v rtccap v rtcbat xin xout [6] [6] [7] [7] nc a 8 xout xin v ss dq6 dq5 dq4 v cc a 13 dq3 a 12 dq2 dq1 dq0 oe a 9 ce nc a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 11 a 7 a 14 a 15 a 16 nc nc nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 a 10 v rtcbat we dq7 hsb int v ss v cc v cap v rtccap 45 46 47 48 nc nc nc nc 48- pin ssop ( 8) [5] [4] [4] [5] top view (not to scale) (not to scale) (not to scale) top view top view notes 4. address expansion for 2-mbit. nc pin not connected to die. 5. address expansion for 4-mbit. nc pin not connected to die. 6. address expansion for 8-mbit. nc pin not connected to die. 7. address expansion for 16-mbit . nc pin not connected to die. cy14b101ka cy14b101ma document number: 001-42880 rev. *k page 4 of 34 pin definitions pin name i/o type description a 0 ?a 16 input address inputs. used to select one of the 131,072 bytes of the nvsram for 8 configuration. a 0 ?a 15 address inputs. used to select one of the 65, 536 words of the nvsram for 16 configuration. dq 0 ?dq 7 input/output bidirectional data i/o lines for 8 configuration. us ed as input or output lines depending on operation. d q 0 ? dq 15 bidirectional data i/o lines for 16 configuration. used as input or output lines depending on operation. nc no connect no connects. this pi n is not connected to the die. we input write enable input, active low. when the chip is enabled and we is low, data on the i/o pins is written to the specific address location. ce input chip enable input, active low. when low, selects the chip. when high, deselects the chip. oe input output enable, active low. the active low oe input enables the data output buffers during read cycles. deasserting oe high causes the i/o pins to tristate. bhe input byte high enable, active low. controls dq 15 ?dq 8 . ble input byte low enable, active low. controls dq 7 ?dq 0 . x out [8] output crystal connection. drives crystal on start up. x in [8] input crystal connection. for 32.768 khz crystal. v rtccap [8] power supply capacitor supplied backup rtc supply voltage. left unconnected if v rtcbat is used. v rtcbat [8] power supply battery supplied backup rtc supply voltage. left unconnected if v rtccap is used. int [8] output interrupt output. programmable to respond to the clock alarm, the watchdog timer, and the power monitor. also programmable to either active high (push or pull) or low (open drain). v ss ground ground for the device. must be connected to the ground of the system. v cc power supply power supply inputs to the device. 3.0 v +20%, ?10% hsb input/output hardware store busy (hsb ). when low this output indicates that a hardware store is in progress. when pulled low external to the chip it initiates a nonvolatile store operation. after each hardware and software store operation hsb is driven high for short time (t hhhd ) with standard output high current and then weak internal pull-up resistor keeps this pin high (external pu ll-up resistor connection optional). v cap power supply autostore capacitor. supplies power to the nvsram during power loss to store data from sram to nonvolatile elements. note 8. left unconnected if rtc feature is not used. cy14b101ka cy14b101ma document number: 001-42880 rev. *k page 5 of 34 device operation the cy14b101ka/cy14b101ma nvsram is made up of two functional components paired in the same physical cell. these are a sram memory cell and a nonvolatile quantumtrap cell. the sram memory cell operates as a standard fast static ram. data in the sram is transferr ed to the nonvolatile cell (the store operation), or from the nonvolatile cell to the sram (the recall operation). using this unique architecture, all cells are stored and recalled in parallel. during the store and recall operations sram read and write operations are inhibited. the cy14b101ka/cy14b101ma supports infinite reads and writes similar to a typical sram. in addition, it provides infinite recall operations from the nonvolatile cells and up to 1 million store operations. see truth table for sram operations on page 25 for a complete description of read and write modes. sram read the cy14b101ka/cy14b101ma performs a read cycle whenever ce and oe are low, and we and hsb are high. the address specified on pins a 0?16 or a 0?15 determines which of the 131,072 data bytes or 65,536 words of 16 bits each are accessed. byte enables (bhe , ble ) determine which bytes are enabled to the output, in the case of 16-bit words. when the read is initiated by an address transition, the outputs are valid after a delay of t aa (read cycle #1). if the read is initiated by ce or oe , the outputs are valid at t ace or at t doe , whichever is later (read cycle #2). the data output repeatedly responds to address changes within the t aa access time without the need for transitions on any control input pins. this remains valid until another address change or until ce or oe is brought high, or we or hsb is brought low. sram write a write cycle is performed when ce and we are low and hsb is high. the address inputs must be stable before entering the write cycle and must re main stable until ce or we goes high at the end of the cycle. the da ta on the common i/o pins io 0?7 are written into the memory if it is valid t sd before the end of a we- controlled write, or before the end of an ce -controlled write. the byte enable inputs (bhe , ble ) determine which bytes are written, in the case of 16-bit wo rds. it is recommended that oe be kept high during the entire write cycle to avoid data bus contention on common i/o lines. if oe is left low, internal circuitry turns off the output buffers t hzwe after we goes low. autostore operation the cy14b101ka/cy14b101ma stores data to the nvsram using one of three storage operations. these three operations are: hardware store, activated by the hsb ; software store, activated by an address sequence; autostore, on device power-down. the autostore oper ation is a unique feature of quantumtrap technology and is enabled by default on the cy14b101ka/cy14b101ma. during a normal operation, the device draws current from v cc to charge a capacitor connected to the v cap pin. this stored charge is used by the chip to perform a single store operation. if the voltage on the v cc pin drops below v switch , the part automatically disconnects the v cap pin from v cc . a store operation is initiated with power provided by the v cap capacitor. note if the capacitor is not connected to v cap pin, autostore must be disabled using the soft sequence specified in preventing autostore on page 7 . in case autostore is enabled without a capacitor on v cap pin, the device attempts an autostore operation without sufficient char ge to complete the store. this corrupts the data stored in nvsram. figure 2. autostore mode figure 2 shows the proper connection of the storage capacitor (v cap ) for automatic stor e operation. see dc electrical characteristics on page 16 for the size of the v cap . the voltage on the v cap pin is driven to v cc by a regulator on the chip. a pull-up should be placed on we to hold it inactive during power-up. this pull-up is only effective if the we signal is tristate during power-up. many mpus tristate their controls on power-up. this should be verified when using the pull-up. when the nvsram comes out of power- on-recall, the mpu must be active or the we held inactive until the mpu comes out of reset. to reduce unnecessary nonvolatile stores, autostore and hardware store operations are ignored unless at least one write operation has taken place since the most recent store or recall cycle. software initiat ed store cycles are performed regardless of whether a write operation has taken place. the hsb signal is monitored by th e system to detect if an autostore cycle is in progress. hardware store (hsb ) operation the cy14b101ka/cy14b101ma provides the hsb pin to control and acknowledge the store operations. the hsb pin is used to request a hardware store cycle. when the hsb pin is driven low, the cy14b101ka/cy14b101ma conditionally initiates a store operation after t delay . an actual store cycle begins only if a write to the sr am has taken place since the last store or recall cycle. the hsb pin also acts as an open drain driver (internal 100 k ? weak pull-up resistor) that is internally driven low to indicate a busy condition when the store (initiated by any means) is in progress. note after each hardware and software store operation hsb is driven high for a short time (t hhhd ) with standard output high 0.1 uf v cc 10 kohm v cap we v cap v ss v cc cy14b101ka cy14b101ma document number: 001-42880 rev. *k page 6 of 34 current and then remains high by internal 100 k ? pull-up resistor. sram write operations that are in progress when hsb is driven low by any means are given time (t delay ) to complete before the store operation is initiat ed. however, any sram write cycles requested after hsb goes low are inhibited until hsb returns high. in case the write latch is not set, hsb is not driven low by the cy14b101ka/cy14b101ma. but any sram read and write cycles are inhibited until hsb is returned high by mpu or other external source. during any store operation, rega rdless of how it is initiated, the cy14b101ka/cy14b101ma c ontinues to drive the hsb pin low, releasing it only when the store is complete. upon completion of the store operation, the nvsram memory access is inhibited for t lzhsb time after hsb pin returns high. leave the hsb unconnected if it is not used. hardware recall (power-up) during power-up or after any low power condition (v cc cy14b101ka cy14b101ma document number: 001-42880 rev. *k page 8 of 34 data protection the cy14b101ka/cy14b101ma prot ects data from corruption during low voltage conditions by inhibiting all externally initiated store and write operations. the low voltage condition is detected when v cc is less than v switch . if the cy14b101ka/cy14b101ma is in a write mode (both ce and we are low) at power-up, after a recall or store, the write is inhibited until the sram is enabled after t lzhsb (hsb to output active). this protects against i nadvertent writes during power-up or brown out conditions. noise considerations see cy application note an1064 . real time clock operation nvtime operation the cy14b101ka/cy14b101ma offers internal registers that contain clock, alarm, watchdog, interrupt, and control functions. rtc registers use the last 16 address locations of the sram. internal double buffering of the clock and timer information registers prevents accessing transitional internal clock data during a read or write oper ation. double buffering also circumvents disrupting normal timing counts or the clock accuracy of the internal clock when accessing clock data. clock and alarm registers store data in bcd format. rtc functionality is described with respect to cy14b101ka in the following sections. the same description applies to cy14b101ma, except for the rtc register addresses. the rtc register addresses for cy14b 101ka range from 0x1fff0 to 0x1ffff, while those for cy14b101ma range from 0x0fff0 to 0x0ffff. see table 3 on page 12 and table 4 on page 13 for a detailed register map description. clock operations the clock registers maintain time up to 9,999 years in one-second increments. the time can be set to any calendar time and the clock automatically keeps track of days of the week and month, leap years, and cent ury transitions. there are eight registers dedicated to the clock functions, which are used to set time with a write cycle and to read time with a read cycle. these registers contain the time of day in bcd format. bits defined as ?0? are currently not used and are reserved for future use by cypress. reading the clock the double buffered rtc register structure reduces the chance of reading incorrect data from the clock. internal updates to the cy14b101ka time keeping registers are stopped when the read bit ?r? (in the flags register at 0x1fff0) is set to ?1? before reading clock data to prevent reading of data in transition. stopping the register updates does not affect clock accuracy. when a read sequence of rtc devi ce is initiated, the update of the user timekeeping registers stop s and does not restart until a ?0? is written to the read bit ?r? (i n the flags register at 0x1fff0). after the end of read sequence, all the rtc registers are simul- taneously updated within 20 ms. setting the clock a write access to the rtc device stops updates to the time keeping registers and enables the time to be set when the write bit ?w? (in the flags register at 0x1fff0) is set to ?1?. the correct day, date, and time is then writ ten into the registers and must be in 24 hour bcd format. the time written is referred to as the ?base time?. this value is st ored in nonvolatile registers and used in the calculation of the current time. when the write bit ?w? is cleared by writing ?0? to it , the values of timekeeping registers are transferred to the actual clock counters after which the clock resumes normal operation. if the time written to the timekeeping registers is not in the correct bcd format, each invalid nibble of the rtc registers continue counting to 0xf before rolling over to 0x0 after which rtc resumes normal operation. note after ?w? bit is set to ?0?, values written into the timekeeping, alarm, calibration, and interrupt registers are transferred to the rtc time keeping counters in t rtcp time. these counter values must be saved to nonvolatile memory either by initiating a software/hardware store or autostore operation. while working in autostore disabled mode, perform a store operation after t rtcp time while writing into the rtc registers for the modifications to be correctly recorded. backup power the rtc in the cy14b101ka is intended for permanently powered operation. the v rtccap or v rtcbat pin is connected depending on whether a capacitor or battery is chosen for the application. when the primary power, v cc , fails and drops below v switch the device switches to the backup power supply. the clock oscillator uses very little current, which maximizes the backup time available from the backup source. regardless of the clock operation with the primary source removed, the data stored in the nvsram is secure, having been stored in the nonvolatile elements when power was lost. during backup operation, the cy14b101ka consumes a 0.35 a (typ) at room temper ature. the user must choose capacitor or battery values according to the application. backup time values based on maximum current specifications are shown in the following table 2 . nominal backup times are approximately two times longer. using a capacitor has the obvious advantage of recharging the backup source each time the syst em is powered up. if a battery is used, a 3 v lithium is recommended and the cy14b101ka sources current only from the battery when the primary power is removed. however, the battery is not recharged at any time by the cy14b101ka. the battery capacity must be chosen for total anticipated cumulative down time required over the life of the system. table 2. rtc backup time capacitor value backup time 0.1 f 72 hours 0.47 f 14 days 1.0 f 30 days cy14b101ka cy14b101ma document number: 001-42880 rev. *k page 9 of 34 stopping and starting the oscillator the oscen bit in the calibration register at 0x1fff8 controls the enable and disable of the oscill ator. this bit is nonvolatile and is shipped to customers in the ? enabled? (set to ?0?) state. to preserve the battery life when the system is in storage, oscen must be set to ?1?. this turns off the oscillator circuit, extending the battery life. if the oscen bit goes from disabled to enabled, it takes approximately one second (two seconds maximum) for the oscillator to start. while system power is off, if the voltage on the backup supply (v rtccap or v rtcbat ) falls below their respective minimum level, the oscillator may fail.the cy14b101ka has the ability to detect oscillator failure when system power is restor ed. this is recorded in the oscillator fail flag (oscf) of the flags register at the address 0x1fff0. when the device is powered on (v cc goes above v switch ) the oscen bit is checked for the ?enabled? status. if the oscen bit is enabled and the oscillator is not active within the first 5 ms, the oscf bi t is set to ?1?. the system must check for this condition and then write ?0? to clear the flag. note that in addition to setting the oscf flag bit, the time registers are reset to the ?base time?, which is the value last written to the timekeeping regist ers. the control or calibration registers and the oscen bit are not affected by the ?oscillator failed? condition. the value of oscf must be reset to ?0? when the time registers are written for the first time. this initializes the state of this bit which may have become set when the system was first powered on. to reset oscf, set the write bit ?w? (in the flags register at 0x1fff0) to a ?1? to enable writes to the flags register . write a ?0? to the oscf bit and then reset the write bit to ?0? to disable writes. calibrating the clock the rtc is driven by a quartz controlled crystal with a nominal frequency of 32.768 khz. clock accuracy depends on the quality of the crystal and calibration. the crystals available in market typically have an error of + 20 ppm to + 35 ppm. however, cy14b101ka employs a calibration circuit that improves the accuracy to +1/?2 ppm at 25 c. this implies an error of +2.5 seconds to ?5 seconds per month. the calibration circuit adds or subt racts counts from the oscillator divider circuit to achieve this accuracy. the number of pulses that are suppressed (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five calibration bits found in calibra tion register at 0x1fff8. the calibration bits occupy the five lo wer order bits in the calibration register. these bits are set to represent any value between ?0? and 31 in binary form. bit d5 is a sign bit, where a ?1? indicates positive calibration and a ?0? indicates negative calibration. adding counts speeds the clock up and subtracting counts slows the clock down. if a binary ?1? is loaded into the register, it corre- sponds to an adjustment of 4.068 or ?2.034 ppm offset in oscil- lator error, depending on the sign. calibration occurs within a 64-minute cycl e. the first 62 minutes in the cycle may, once every minute, have one second shortened by 128 or lengthened by 256 oscillator cycles. if a binary ?1? is loaded into the register, only the first two minutes of the 64-minute cycle are modified. if a binary 6 is loaded, the first 12 are affected, and so on. therefor e, each calibration step has the effect of adding 512 or subtractin g 256 oscillator cycles for every 125,829,120 ac tual oscillator cycles, that is, 4.068 or ?2.034 ppm of adjustment per calibration step in the calibration register. to determine the required calibration, the cal bit in the flags register (0x1fff0) must be set to ?1?. this causes the int pin to toggle at a nominal frequency of 512 hz. any deviation measured from the 512 hz indicates the degree and direction of the required correction. for example, a reading of 512.01024 hz indicates a +20 ppm error. hence, a decimal value of ?10 (001010b) must be loaded into the calibration register to offset this error. note setting or changing the calibration register does not affect the test output frequency. to set or clear cal, set the write bit ?w? (in the flags register at 0x1fff0) to ?1? to enable writes to the flags register . write a value to cal, and then reset the write bit to ?0? to disable writes. alarm the alarm function compares user programmed values of alarm time and date (stored in the registers 0x1fff1-5) with the corre- sponding time of day and date values. when a match occurs, the alarm internal flag (af) is set and an interrupt is generated on int pin if alarm interrupt enable (aie) bit is set. there are four alarm match fields ? date, hours, minutes, and seconds. each of these fields has a match bit that is used to determine if the field is used in the alarm match logic. setting the match bit to ?0? indicates that the corresponding field is used in the match process. depending on the match bits, the alarm occurs as specifically as once a month or as frequently as once every minute. selecting none of the match bits (all 1s) indicates that no match is required and therefore, alarm is disabled. selecting all match bits (all 0s) causes an exact time and date match. there are two ways to detect an alarm event: by reading the af flag or monitoring the int pin. the af flag in the flags register at 0x1fff0 indicates that a date or time match has occurred. the af bit is set to ?1? when a match occurs. reading the flags register clears the alarm flag bit (and all others). a hardware interrupt pin may also be used to detect an alarm event. to set, clear or enable an alarm, set the ?w? bit (in flags register ? 0x1fff0) to ?1? to enable writes to alarm registers. after writing the alarm value, clear the ?w? bit back to ?0? for the changes to take effect. note cy14b101ka requires the alarm match bit for seconds (bit ?d7? in alarm-seconds register 0x1fff2) to be set to ?0? for proper operation of alarm flag and interrupt. watchdog timer the watchdog timer is a free running down counter that uses the 32 hz clock (31.25 ms) derived from the crystal oscillator. the oscillator must be running for the watchdog to function. it begins counting down from the value loaded in the watchdog timer register. the timer consists of a loadable register and a free running counter. on power-up, the watchdog time out value in register 0x1fff7 is loaded into the counter load register. counting begins on power-up and restarts from the loadable value any time the watchdog strobe (wds) bit is set to ?1?. the counter is cy14b101ka cy14b101ma document number: 001-42880 rev. *k page 10 of 34 compared to the terminal value of ?0?. if the counter reaches this value, it causes an internal flag and an optional interrupt output. you can prevent the time out interrupt by setting wds bit to ?1? prior to the counter reaching ?0?. this causes the counter to reload with the watchdog time out value and to be restarted. as long as the user sets the wds bi t prior to the counter reaching the terminal value, the interrupt and wdt flag never occur. new time out values are written by setting the watchdog write bit to ?0?. when the wdw is ?0?, new writes to the watchdog time out value bits d5?d0 are enabled to modify the time out value. when wdw is ?1?, writes to bits d5-d0 are ignored. the wdw function enables a user to set the wds bit without concern that the watchdog timer value is modified. a logical diagram of the watchdog timer is shown in figure 3 . note that setting the watchdog time out value to ?0? disables the watchdog function. the output of the watchdog timer is the flag bit wdf that is set if the watchdog is allowed to time out. if the watchdog interrupt enable (wie) bit in the interrupt register is set, a hardware interrupt on int pin is also generated on watchdog timeout. the flag and the hardware interrupt are both cleared when the user reads the flags registers. power monitor the cy14b101ka provides a power management scheme with power fail interrupt capability. it also controls the internal switch to backup power for the clock and protects the memory from low v cc access. the power monitor is based on an internal bandgap reference circuit that compares the v cc voltage to v switch threshold. as described in the autostore operation on page 5 , when v switch is reached as v cc decays from power loss, a data store operation is initiated from sram to the nonvolatile elements, securing the last sram data state. power is also switched from v cc to the backup supply (battery or capacitor) to operate the rtc oscillator. when operating from the backup source, read and write operations to nvsram are inhibited and the rtc functions are not available to the user. the rtc clock continues to operate in the background. the updated rtc time keeping registers data are available to the user after v cc is restored to the device (see autostore/power-up recall on page 22 ). interrupts the cy14b101ka has flags register, interrupt register, and interrupt logic that can signal interrupt to the microcontroller. there are three potential sources for interrupt: watchdog timer, power monitor, and alarm timer. each of these can be individually enabled to drive the int pin by appropriate setting in the interrupt register (0x1fff6). in addition, each has an associated flag bit in the flags register (0x1fff0) that the host processor uses to determine the cause of the interrupt. the int pin driver has two bits that specify its behavior when an interrupt occurs. an interrupt is raised only if both a flag is raised by one of the three sources and the respective interrupt enable bit in interrupts register is enabled (set to ?1?). after an interrupt source is active, two programmable bits, h/l and p/l, determine the behavior of the output pin driver on int pin. these two bits are located in the interrupt register and can be us ed to drive level or pulse mode output from the int pin. in pulse mode, the pulse width is internally fixed at approximatel y 200 ms. this mode is intended to reset a host microcontroller. in the level mode, the pin goes to its active polarity until the flags register is read by the user. this mode is used as an interrupt to a host microcontroller. the control bits are summarized in the following section. interrupts are only generated while working on normal power and are not triggered when system is running in backup power mode. note cy14b101ka generates valid interrupts only after the power-up recall sequence is comple ted. all events on int pin must be ignored for t hrecall duration after power-up. interrupt register watchdog interrupt enable (wie) . when set to ?1?, the watchdog timer drives the int pin and an internal flag when a watchdog time out occurs. when wie is set to ?0?, the watchdog timer only affects the wdf flag in flags register . alarm interrupt enable (aie) . when set to ?1?, the alarm match drives the int pin and an internal flag. when aie is set to ?0?, the alarm match only affects the af flag in flags register . power fail interr upt enable (pfe) . when set to ?1?, the power fail monitor drives the pin and an internal flag. when pfe is set to ?0?, the power fail monitor only affects the pf flag in flags register. high/low (h/l) . when set to a ?1?, the int pin is active high and the driver mode is push pull. the int pin drives high only when v cc is greater than v switch . when set to a ?0?, the int pin is active low and the drive mode is open drain. the int pin must be pulled up to vcc by a 10 k resistor while using the interrupt in active low mode. pulse/level (p/l) . when set to a ?1? and an interrupt occurs, the int pin is driven for approximately 200 ms. when p/l is set to a ?0?, the int pin is driven high or low (determined by h/l) until the flags register is read. when an enabled interrupt source activates the int pin, an external host reads the flags r egisters to determine the cause. all flags are cleared when the regi ster is read. if the int pin is programmed for level mode, then the condition clears and the int pin returns to its inactive state. if the pin is programmed for pulse mode, then reading the flag also clears the flag and the pin. the pulse does not complete its specified duration if the flags register is read. if the int pin is used as a host reset, then the flags register is not read during a reset. figure 3. watchdog timer block diagram 1 hz oscillator clock divider counter zero compare wdf wds load register wdw d q q watchdog register write to watchdog register 32 hz 32,768 khz cy14b101ka cy14b101ma document number: 001-42880 rev. *k page 11 of 34 flags register the flags register has three flag bits: wdf, af, and pf, which can be used to generate an interrupt. these flags are set by the watchdog timeout, alarm match, or power fail monitor respectively. the processor can either poll this register or enable interrupts to be informed when a flag is set. these flags are automatically reset when the register is read. the flags register is automatically loaded with the value 0x00 on power-up (except for the oscf bit; see stopping and starting the oscillator on page 9 ). figure 4. rtc recommended component configuration [12] x out x in y1 c2 c1 recommended values y 1 = 32.768 khz (12.5 pf) c 1 = 10 pf c 2 = 67 pf note: the recommended values for c1 and c2 include board trace capacitance. figure 5. interrupt block diagram wdf - watchdog timer flag wie - watchdog interrupt pf - power fail flag pfe - power fail enable af - alarm flag aie - alarm interrupt enable p/l - pulse level h/l - high/low enable watchdog timer power monitor clock alarm vint wdf wie pf pfe af aie p/l pin driver h/l int v cc v ss note 12. for nonvolatile static random access memory (nvsram) real time clock (rtc) design guidelines and best practices, see applica tion note an61546. cy14b101ka cy14b101ma document number: 001-42880 rev. *k page 12 of 34 table 3. rtc register map [13, 14, 15] register bcd format data [14] function/range cy14b101ka cy14b101ma d7 d6 d5 d4 d3 d2 d1 d0 0x1ffff 0x0ffff 10s years years years: 00?99 0x1fffe 0x0fffe 0 0 0 10s months months months: 01?12 0x1fffd 0x0fffd 0 0 10s day of month d ay of month day of month: 01?31 0x1fffc 0x0fffc 0 0 0 0 0 day of week day of week: 01?07 0x1fffb 0x0fffb 0 0 10s hours hours hours: 00?23 0x1fffa 0x0fffa 0 10s minutes minutes minutes: 00?59 0x1fff9 0x0fff9 0 10s seconds seconds seconds: 00?59 0x1fff8 0x0fff8 oscen (0) 0cal sign (0) calibration (00000) calibration values [16] 0x1fff7 0x0fff7 wds (0) wdw (0) wdt (000000) watchdog [16] 0x1fff6 0x0fff6 wie (0) aie (0) pfe (0) 0 h/l (1) p/l (0) 0 0 interrupts [16] 0x1fff5 0x0fff5 m (1) 0 10s alarm date alarm day alarm, day of month: 01?31 0x1fff4 0x0fff4 m (1) 0 10s alarm hours alarm hours alarm, hours: 00?23 0x1fff3 0x0fff3 m (1) 10s alarm minutes alarm minutes alarm, minutes: 00?59 0x1fff2 0x0fff2 m (1) 10s alarm seconds alarm, seconds alarm, seconds: 00?59 0x1fff1 0x0fff1 10s centuries centuries centuries: 00?99 0x1fff0 0x0fff0 wdf af pf oscf [17] 0cal (0) w (0) r (0) flags [16] notes 13. upper byte d15 ? d8 (cy14b101ma) of rtc registers are reserved for future use. 14. the unused bits of rtc registers are reserved for future use and should be set to ?0?. 15. () designates values shipped from the factory. 16. this is a binary value, not a bcd value. 17. when user resets oscf flag bit, the flags register will be updated after t rtcp time. cy14b101ka cy14b101ma document number: 001-42880 rev. *k page 13 of 34 table 4. register map detail register description cy14b101ka cy14b101ma 0x1ffff 0x0ffff time keeping - years d7 d6 d5 d4 d3 d2 d1 d0 10s years years contains the lower two bcd digits of the year. low er nibble (four bits) contains the value for years; upper nibble (four bits) contains the value for 10s of years. each nibble operates from 0 to 9. the range for the register is 0?99. 0x1fffe 0x0fffe time keeping - months d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 10s month months contains the bcd digits of the mo nth. lower nibble (four bits) contains the lower digit and operates from 0 to 9; upper nibble (one bit) contains the upper digit and operates from 0 to 1. the range for the register is 1?12. 0x1fffd 0x0fffd time keeping - date d7 d6 d5 d4 d3 d2 d1 d0 0 0 10s day of month day of month contains the bcd digits for the dat e of the month. lower nibble (four bits) contains the lower digit and operates from 0 to 9; upper ni bble (two bits) contains the 10s digit and operates from 0 to 3. the range for the register is 1?31. leap years are automatically adjusted for. 0x1fffc 0x0fffc time keeping - day d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 day of week lower nibble (three bits) contains a value that correlates to day of the week. day of the week is a ring counter that counts from 1 to 7 then returns to 1. the user must assign meaning to the day value, because the day is not integrated with the date. 0x1fffb 0x0fffb time keeping - hours d7 d6 d5 d4 d3 d2 d1 d0 0 0 10s hours hours contains the bcd value of hours in 24 hour format. lower nibble (four bits) contains the lower digit and operates from 0 to 9; upper nibble (t wo bits) contains the upper digit and operates from 0 to 2. the range for the register is 0?23. 0x1fffa 0x0fffa time keeping - minutes d7 d6 d5 d4 d3 d2 d1 d0 0 10s minutes minutes contains the bcd value of minutes. lower nibble (four bits) contains the lower digit and operates from 0 to 9; upper nibble (three bits) contains the upper minutes digit and operates from 0 to 5. the range for the register is 0?59. 0x1fff9 0x0fff9 time keeping - seconds d7 d6 d5 d4 d3 d2 d1 d0 0 10s seconds seconds contains the bcd value of seconds. lower nibble (four bits) contains the lower digit and operates from 0 to 9; upper nibble (three bits) contains th e upper digit and operates from 0 to 5. the range for the register is 0?59. cy14b101ka cy14b101ma document number: 001-42880 rev. *k page 14 of 34 register description cy14b101ka cy14b101ma 0x1fff8 0x0fff8 calibration/control d7 d6 d5 d4 d3 d2 d1 d0 oscen 0 calibration sign calibration oscen oscillator enable. when set to ?1?, the oscillator is stopped. when set to ?0?, the oscillator runs. disabling the oscillator saves battery or capacitor power during storage. calibration sign determines if the calibr ation adjustment is applied as an addit ion (1) to or as a subtraction (0) from the time-base. calibration these five bits cont rol the calibration of the clock. 0x1fff7 0x0fff7 watchdog timer d7 d6 d5 d4 d3 d2 d1 d0 wds wdw wdt wds watchdog strobe. setting this bit to ?1? reloads and restarts the watchdog timer. setting the bit to ?0? has no effect. the bit is cleared automatically after the watchdog timer is reset. the wds bit is write only. reading it always returns a 0. wdw watchdog write enable. setting this bit to 1 disables any write to the watchdog timeout value (d5?d0). this allows the user to set the watchdog strobe bit without disturbing the timeout value. setting this bit to ?0? allows bits d5?d0 to be wr itten to the watchdog regist er when the next write cycle is complete. this function is explained in more detail in watchdog timer on page 9 . wdt watchdog timeout selection. the watchdog timer interval is selected by the 6-bit value in this register. it represents a multiplier of the 32 hz count (31.25 ms). the range of timeout value is 31.25 ms (a setting of 1) to 2 seconds (setting of 3 fh). setting the watchdog timer register to 0 disables the timer. these bits can be written only if the wdw bit was set to 0 on a previous cycle. 0x1fff6 0x0fff6 interrupt status/control d7 d6 d5 d4 d3 d2 d1 d0 wie aie pfe 0 h/l p/l 0 0 wie watchdog interrupt enable. when set to ?1? and a watchdog timeout occurs, the watchdog timer drives the int pin and the wdf flag. when set to ?0?, the watchdog timeout affects only the wdf flag. aie alarm interrupt enable. when set to ?1?, the al arm match drives the int pin and the af flag. when set to ?0?, the alarm match only affects the af flag. pfe power fail enable. when set to ?1?, the power fail monitor drives the int pin and the pf flag. when set to ?0?, the power fail monitor affects only the pf flag. 0 reserved for future use h/l high/low. when set to ?1?, the int pin is driven active high. when set to ?0?, the int pin is open drain, active low. p/l pulse/level. when set to ?1?, the int pin is driven active (determined by h/l) by an interrupt source for approximately 200 ms. when set to ?0?, the int pin is driven to an active level (as set by h/l) until the flags register is read. 0x1fff5 0x0fff5 alarm - day d7 d6 d5 d4 d3 d2 d1 d0 m 0 10s alarm date alarm date contains the alarm value for the date of the month and the mask bit to select or deselect the date value. m match. when this bit is set to ?0?, the date value is used in the alarm match. setting this bit to ?1? causes the match circuit to ignore the date value. table 4. register map detail (continued) cy14b101ka cy14b101ma document number: 001-42880 rev. *k page 15 of 34 register description cy14b101ka cy14b101ma 0x1fff4 0x0fff4 alarm - hours d7 d6 d5 d4 d3 d2 d1 d0 m 0 10s alarm hours alarm hours contains the alarm value for the hours and the mask bit to select or deselect the hours value. m match. when this bit is set to ?0?, the hours value is used in the alarm match. setting this bit to ?1? causes the match circuit to ignore the hours value. 0x1fff3 0x0fff3 alarm - minutes d7 d6 d5 d4 d3 d2 d1 d0 m 10s alarm minutes alarm minutes contains the alarm value for the minutes and the mask bit to select or deselect the minutes value. m match. when this bit is set to ?0?, the minutes value is used in the alarm match. setting this bit to ?1? causes the match circuit to ignore the minutes value. 0x1fff2 0x0fff2 alarm - seconds d7 d6 d5 d4 d3 d2 d1 d0 m 10s alarm seconds alarm seconds contains the alarm value for the seconds and the mask bit to select or deselect the seconds? value. m match. when this bit is set to ?0?, the seconds va lue is used in the alarm match. setting this bit to ?1? causes the match circuit to ignore the seconds value. 0x1fff1 0x0fff1 time keeping - centuries d7 d6 d5 d4 d3 d2 d1 d0 10s centuries centuries contains the bcd value of centuries. lower nibbl e contains the lower digit and operates from 0 to 9; upper nibble contains the upper digit and oper ates from 0 to 9. the range for the register is 0?99 centuries. 0x1fff0 0x0fff0 flags d7 d6 d5 d4 d3 d2 d1 d0 wdf af pf oscf 0 cal w r wdf watchdog timer flag. this read only bit is set to ?1? when the watchdog timer is allowed to reach 0 without being reset by the user. it is cleared to 0 when the flags register is read or on power-up af alarm flag. this read only bit is set to ?1? when the time and date match the values stored in the alarm registers with the match bits = 0. it is clea red when the flags register is read or on power-up. pf power fail flag. this read only bit is set to ?1? when power falls below the power fail threshold v switch . it is cleared to 0 when the flags register is read or on power-up. oscf oscillator fail flag. set to ?1? on power-up if th e oscillator is enabled and not running in the first 5 ms of operation. this indicates that rtc backup power failed and clock value is no longer valid. this bit survives the power cycle and is never clea red internally by the chip. the user must check for this condition and write '0' to clear this fl ag. when user resets oscf flag bit, the bit will be updated after t rtcp time. cal calibration mode. when set to ?1?, a 512 hz sq uare wave is output on t he int pin. when set to ?0?, the int pin resumes normal operation. this bit defaults to ?0? (disabled) on power-up. w write enable: setting the ?w? bit to ?1? freezes updates of the rtc regist ers. the user can then write to rtc registers, alarm registers, calibrati on register, interrupt register and flags register. setting the ?w? bit to ?0? causes the contents of the rtc registers to be transferred to the time keeping counters if the time has chan ged. this transfer process takes t rtcp time to complete. this bit defaults to 0 on power-up. r read enable: setting ?r? bit to ?1?, stops clock up dates to user rtc registers so that clock updates are not seen during the reading process. set ?r? bit to ?0? to resume clock updates to the holding register. setting this bit does not require ?w? bit to be set to ?1?. this bit defaults to 0 on power-up. table 4. register map detail (continued) cy14b101ka cy14b101ma document number: 001-42880 rev. *k page 16 of 34 maximum ratings exceeding maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature ..... ............ ............... ?65 ? c to +150 ? c maximum accumulated storage time at 150 ? c ambient temperature ...................... 1000 h at 85 ? c ambient temperature .................... 20 years maximum junction temperature .................................. 150 ? c supply voltage on v cc relative to v ss ...........?0.5 v to 4.1 v voltage applied to outputs in high z state .................................... ?0.5 v to v cc + 0.5 v input voltage ....................................... ?0.5 v to v cc + 0.5 v transient voltage (< 20 ns) on any pin to ground potential ................. ?2.0 v to v cc + 2.0 v package power dissipation capability (t a = 25 c) ................................................. 1.0 w surface mount pb soldering temperature (3 seconds) ........ .............. .............. ..... +260 ? c dc output current (1 output at a time, 1s duration) .... 15 ma static discharge voltage (per mil-std-883, method 3015) .............. ........... > 2001 v latch up current ............................................... ..... > 200 ma operating range range ambient temperature v cc industrial ?40 ? c to +85 ? c 2.7 v to 3.6 v dc electrical characteristics over the operating range parameter description test conditions min typ [18] max unit v cc power supply voltage 2.7 3.0 3.6 v i cc1 average v cc current t rc = 25 ns t rc = 45 ns values obtained without output loads (i out = 0 ma) ??70 52 ma ma i cc2 average v cc current during store all inputs don?t care, v cc = max. average current for duration t store ??10ma i cc3 [18] average v cc current at t rc = 200 ns, v cc(typ) , 25 c all inputs cycling at cmos levels. values obtained without output loads (i out = 0 ma). ?35?ma i cc4 average v cap current during autostore cycle all inputs don?t care. average current for duration t store ??5ma i sb v cc standby current ce > (v cc ? 0.2 v). v in < 0.2 v or > (v cc ? 0.2 v). w bit set to ?0?. standby current level after nonvolatile cycle is complete. inputs are static. f = 0 mhz. ??5ma i ix [19] input leakage current (except hsb ) v cc = max, v ss < v in < v cc ?1 ? +1 a input leakage current (for hsb )v cc = max, v ss < v in < v cc ?100 ? +1 a i oz off state output leakage current v cc = max, v ss < v out < v cc , ce or oe > v ih or bhe /ble > v ih or we < v il ?1 ? +1 a v ih input high voltage 2.0 ? v cc + 0.5 v v il input low voltage v ss ? 0.5 ? 0.8 v v oh output high voltage i out = ?2 ma 2.4 ? ? v v ol output low voltage i out = 4 ma ? ? 0.4 v notes 18. typical values are at 25 c, v cc = v cc(typ) . not 100% tested. 19. the hsb pin has i out = ?2 a for v oh of 2.4 v when both active high and low drivers are disabled. when they are enabled standard v oh and v ol are valid. this parameter is characterized but not tested. cy14b101ka cy14b101ma document number: 001-42880 rev. *k page 17 of 34 v cap [20] storage capacitor between v cap pin and v ss 61 68 180 f v vcap [21, 22] maximum voltage driven on v cap pin by the device v cc = max ? ? v cc v dc electrical characteristics (continued) over the operating range parameter description test conditions min typ [18] max unit data retention and endurance over the operating range parameter description min unit data r data retention 20 years nv c nonvolatile store operations 1,000 k capacitance parameter [22] description test conditions max unit c in input capacitance (except bhe , ble and hsb )t a = 25 ? c, f = 1 mhz, v cc = v cc(typ) 7pf input capacitance (for bhe , ble and hsb )8pf c out output capacitance (except hsb ) 7 pf output capacitance (for hsb ) 8 pf thermal resistance parameter [22] description test conditions 48-pin ssop 44-pin tsop ii 54-pin tsop ii unit ? ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with eia/jesd51. 37.47 41.74 36.4 ? c/w ? jc thermal resistance (junction to case) 24.71 11.90 10.13 ? c/w notes 20. min v cap value guarantees that there is a sufficient charge ava ilable to complete a successful autostore operation. max v cap value guarantees that the capacitor on v cap is charged to a minimum voltage during a power-up recall cycle so that an immediate power-down cycle can complete a successful autostore. therefore it is always recommended to use a capacitor within the specified min and max limits. see application note an43593 for more details on v cap options. 21. maximum voltage on v cap pin (v vcap ) is provided for guidance when choosing the v cap capacitor. the voltage rating of the v cap capacitor across the operating temperature range should be higher than the v vcap voltage. 22. these parameters are guaranteed by design and are not tested. cy14b101ka cy14b101ma document number: 001-42880 rev. *k page 18 of 34 ac test conditions input pulse levels ...................................................0 v to 3 v input rise and fall times (10%?90%) ........................... < 3 ns input and output timing reference levels ....................... 1.5 v ac test loads figure 6. ac test loads 3.0 v output 5 pf r1 r2 789 ? 3.0 v output 30 pf r1 r2 789 ? 577 ? 577 ? over the operating range parameter description min typ [23] max units v rtcbat rtc battery pin voltage 1.8 3.0 3.6 v i bak [24] rtc backup current t a (min) ? ? 0.35 a 25 c ? 0.35 ? a t a (max) ? ? 0.5 a v rtccap [25] rtc capacitor pin voltage t a (min) 1.6 ? 3.6 v 25 c 1.5 3.0 3.6 v t a (max) 1.4 ? 3.6 v tocs rtc oscillator time to start ? 1 2 sec t rtcp rtc processing time from end of ?w? bit set to ?0? ? ? 350 s r bkchg rtc backup capacitor charge current-limiting resistor 350 ? 850 ? notes 23. these parameters are guaranteed by design and are not tested. 24. from either v rtccap or v rtcbat . 25. if v rtccap > 0.5 v or if no capacitor is connected to v rtccap pin, the oscillator starts in t ocs time. if a backup capacitor is connected and v rtccap < 0.5 v, the capacitor must be allowed to charge to 0.5 v for oscillator to start. cy14b101ka cy14b101ma document number: 001-42880 rev. *k page 19 of 34 ac switching characteristics over the operating range parameters [26] description 25 ns 45 ns unit cypress parameter alt parameter min max min max sram read cycle t ace t acs chip enable access time ? 25 ? 45 ns t rc [27] t rc read cycle time 25 ? 45 ? ns t aa [28] t aa address access time ? 25 ? 45 ns t doe t oe output enable to data valid ? 12 ? 20 ns t oha [28] t oh output hold after address change 3 ? 3 ? ns t lzce [29, 30] t lz chip enable to output active 3 ? 3 ? ns t hzce [29, 30] t hz chip disable to output inactive ? 10 ? 15 ns t lzoe [29, 30] t olz output enable to output active 0 ? 0 ? ns t hzoe [29, 30] t ohz output disable to output inactive ? 10 ? 15 ns t pu [29] t pa chip enable to power active 0 ? 0 ? ns t pd [29] t ps chip disable to power standby ? 25 ? 45 ns t dbe ? byte enable to data valid ? 12 ? 20 ns t lzbe [29] ? byte enable to output active 0 ? 0 ? ns t hzbe [29] ? byte disable to output inactive ? 10 ? 15 ns sram write cycle t wc t wc write cycle time 25 ? 45 ? ns t pwe t wp write pulse width 20 ? 30 ? ns t sce t cw chip enable to end of write 20 ? 30 ? ns t sd t dw data setup to end of write 10 ? 15 ? ns t hd t dh data hold after end of write 0 ? 0 ? ns t aw t aw address setup to end of write 20 ? 30 ? ns t sa t as address setup to start of write 0 ? 0 ? ns t ha t wr address hold after end of write 0 ? 0 ? ns t hzwe [29, 30, 31] t wz write enable to output disable ? 10 ? 15 ns t lzwe [29, 30] t ow output active after end of write 3 ? 3 ? ns t bw ? byte enable to end of write 20 ? 30 ? ns switching waveforms figure 7. sram read cycle #1 (address controlled) [27, 28, 32] address data output address valid previous data valid output data valid t rc t aa t oha notes 26. test conditions assume signal transition time of 3 ns or less, timing reference levels of v cc /2, input pulse levels of 0 to v cc(typ) , and output loading of the specified i ol /i oh and load capacitance shown in figure 6 on page 18 . 27. we must be high during sram read cycles. 28. device is continuously selected with ce , oe, and bhe /ble low. 29. these parameters are guaranteed by design and are not tested. 30. measured 200 mv from steady state output voltage. 31. if we is low when ce goes low, the outputs remain in the high impedance state. 32. hsb must remain high during read and write cycles. cy14b101ka cy14b101ma document number: 001-42880 rev. *k page 20 of 34 figure 8. sram read cycle #2 (ce and oe controlled) [33, 34, 35] figure 9. sram write cycle #1 (we controlled) [33, 35, 36, 37] switching waveforms (continued) address valid address data output output data valid standby active high impedance ce oe bhe, ble i cc t hzce t rc t ace t aa t lzce t doe t lzoe t dbe t lzbe t pu t pd t hzbe t hzoe data output data input input data valid high impedance address valid address previous data t wc t sce t ha t bw t aw t pwe t sa t sd t hd t hzwe t lzwe we bhe, ble ce notes 33. bhe and ble are applicable for 16 configuration only. 34. we must be high during sram read cycles. 35. hsb must remain high during read and write cycles. 36. if we is low when ce goes low, the outputs remain in the high impedance state. 37. ce or we must be ?? v ih during address transitions. cy14b101ka cy14b101ma document number: 001-42880 rev. *k page 21 of 34 figure 10. sram write cycle #2 (ce controlled) [38, 39, 40, 41] figure 11. sram write cycle #3 (bhe and ble controlled) [39, 40, 41, 42, 43] switching waveforms (continued) data output data input input data valid high impedance address valid address t wc t sd t hd bhe, ble we ce t sa t sce t ha t bw t pwe data output data input input data valid high impedance address valid address t wc t sd t hd bhe, ble we ce t sce t sa t bw t ha t aw t pwe (not applicable for rtc register writes) notes 38. bhe and ble are applicable for 16 configuration only. 39. if we is low when ce goes low, the outputs remain in the high impedance state. 40. hsb must remain high during read and write cycles. 41. ce or we must be ?? v ih during address transitions. 42. while there are 19 address lines on the cy14b101ka (18 address lines on the cy14b101ma), only 13 address lines (a 14 ?a 2 ) are used to control software modes. the remaining address lines are don?t care. 43. only ce and we controlled writes to rtc registers are allowed. ble pin must be held low before ce or we pin goes low for writes to rtc register. cy14b101ka cy14b101ma document number: 001-42880 rev. *k page 22 of 34 autostore/power-up recall over the operating range parameter description cy14b101ka/cy14b101ma unit min max t hrecall [44] power-up recall duration ? 20 ms t store [45] store cycle duration ? 8 ms t delay [46] time allowed to comple te sram write cycle ? 25 ns v switch low voltage trigger level ? 2.65 v t vccrise [47] v cc rise time 150 ? s v hdis [47] hsb output disable voltage ? 1.9 v t lzhsb [47] hsb to output active time ? 5 s t hhhd [47] hsb high active time ? 500 ns switching waveforms figure 12. autostore or power-up recall [48] v switch v hdis t vccrise t store t store t hhhd t hhhd t delay t delay t lzhsb t lzhsb t hrecall t hrecall hsb out autostore power- up recall read & write inhibited (rwi) power-up recall read & write brown out autostore power-up recall read & write power down autostore note note note note v cc 45 45 49 49 notes 44. t hrecall starts from the time v cc rises above v switch . 45. if an sram write has not taken place since the last nonv olatile cycle, no autostore or hardware store takes place 46. on a hardware store and autostore initiation, sram write operation continues to be enabled for time t delay . 47. these parameters are guaranteed by design and are not tested. 48. read and write cycles are ignored during store, recall, and while v cc is below v switch . 49. during power-up and power-down, hsb glitches when hsb pin is pulled up through an external resistor. cy14b101ka cy14b101ma document number: 001-42880 rev. *k page 23 of 34 software controlled store/recall cycl e over the operating range parameter [50, 51] description 25 ns 45 ns unit min max min max t rc store/recall initiation cycle time 25 ? 45 ? ns t sa address setup time 0 ? 0 ? ns t cw clock pulse width 20 ? 30 ? ns t ha address hold time 0 ? 0 ? ns t recall recall duration ? 200 ? 200 s t ss [52, 53] soft sequence processing time ? 100 ? 100 s switching waveforms figure 13. ce & oe controlled software store/recall cycle [51] figure 14. autostore enable/disable cycle [51] t rc t rc t sa t cw t cw t sa t ha t lzce t hzce t ha t ha t ha t store /t recall t hhhd t lzhsb high impedance address #1 address #6 address ce oe hsb (store only) dq (data) rwi t delay note 54 t rc t rc t sa t cw t cw t sa t ha t lzce t hzce t ha t ha t ha t delay address #1 address #6 address ce oe dq (data) t ss note rwi 54 notes 50. the software sequence is clocked with ce controlled or oe controlled reads. 51. the six consecutive addresses must be read in the order listed in tab l e 1 . we must be high during all six consecutive cycles. 52. this is the amount of time it takes to take action on a soft sequence command. vcc power must remain high to effectively reg ister command. 53. commands such as store and recall lock out i/o until operation is complete which further incr eases this time. see the specif ic command. 54. dq output data at the sixth read may be invalid since the output is disabled at t delay time. cy14b101ka cy14b101ma document number: 001-42880 rev. *k page 24 of 34 hardware store cycle over the operating range parameter description cy14b101ka/cy14b101ma unit min max t dhsb hsb to output active time when write latch not set ? 25 ns t phsb hardware store pulse width 15 ? ns switching waveforms figure 15. hardware store cycle [55] figure 16. soft sequence processing [56, 57] t phsb t phsb t delay t dhsb t delay t store t hhhd t lzhsb write latch set write latch not set hsb (in) hsb (out) dq (data out) rwi hsb (in) hsb (out) rwi hsb pin is driven high to v c c only by internal sram is disabled as long as hsb (in) is driven low . hsb driver is disabled t dhsb 100 kohm resistor, address #1 address #6 address #1 address #6 soft sequence command t ss t ss ce address v cc t sa t cw soft sequence command t cw notes 55. if an sram write has not taken place since the last nonvolatile cycle, no au tostore or hardware store takes place. 56. this is the amount of time it takes to take action on a soft sequence command. v cc power must remain high to effectively register command. 57. commands such as store and recall lock out i/o until operati on is complete which further increases this time. see the specif ic command. cy14b101ka cy14b101ma document number: 001-42880 rev. *k page 25 of 34 truth table for sram operations hsb must remain high for sram operations. table 5. truth table for 8 configuration ce we oe inputs/outputs [58] mode power h x x high z deselect/power-down standby l h l data out (dq 0 ?dq 7 ) read active l h h high z output disabled active l l x data in (dq 0 ?dq 7 ) write active table 6. truth table for 16 configuration ce we oe bhe [59] ble [59] inputs/outputs [58] mode power h x x x x high z deselect/power-down standby l x x h h high z output disabled active lhllldata out (dq 0 ?dq 15 ) read active l h l h l data out (dq 0 ?dq 7 ) dq 8 ?dq 15 in high z read active l h l l h data out (dq 8 ?dq 15 ) dq 0 ?dq 7 in high z read active l h h l l high z output disabled active l h h h l high z output disabled active l h h l h high z output disabled active llxlldata in (dq 0 ?dq 15 ) write active llxhldata in (dq 0 ?dq 7 ) dq 8 ?dq 15 in high z write active llxlhdata in (dq 8 ?dq 15 ) dq 0 ?dq 7 in high z write active notes 58. data dq 0 ?dq 7 for 8 configuration and data dq 0 ?dq 15 for 16 configuration. 59. bhe and ble are applicable for 16 configuration only. cy14b101ka cy14b101ma document number: 001-42880 rev. *k page 26 of 34 ordering code definitions ordering information cypress offers other versions of this type of product in many different configurations an d features. the below table contains o nly the list of parts that are currently available. for a comple te listing of all options, vi sit the cypress website at www.cypress.com and see the product summary page at http://www.cypress.com/products or contact your local sales representative. cypress maintains a worldwide network of offices, solution centers, manufacturer's r epresentatives and distributors. to find the office closest to you, visit us at http://www.cypress.com /go/datasheet/offices . speed (ns) ordering code package diagram package type operating range 25 CY14B101KA-ZS25XIt 51-85087 44-pin tsop ii industrial CY14B101KA-ZS25XI 51-85087 44-pin tsop ii cy14b101ka-sp25xit 51-85061 48-pin ssop cy14b101ka-sp25xi 51-85061 48-pin ssop 45 cy14b101ka-zs45xit 51-85087 44-pin tsop ii cy14b101ka-zs45xi 51-85087 44-pin tsop ii cy14b101ka-sp45xit 51-85061 48-pin ssop cy14b101ka-sp45xi 51-85061 48-pin ssop all the above parts are pb-free. option: t - tape and reel blank - std. speed: 25 - 25 ns data bus: k - 8 + rtc m - 16 + rtc density: 101 - 1 mb voltage: b - 3.0 v cypress cy 14 b 101 k a - zs 25 x i t 14 - nvsram temperature: i - industrial (?40 to 85 c) pb-free 45 - 45 ns die revision: blank - no rev a - first rev sp - 48-pin ssop zs - 44-pin tsop ii package: cy14b101ka cy14b101ma document number: 001-42880 rev. *k page 27 of 34 package diagrams figure 17. 44-pin tsop ii package outline, 51-85087 51-85087 *d cy14b101ka cy14b101ma document number: 001-42880 rev. *k page 28 of 34 figure 18. 54-pin tsop ii (22.4 11.84 1.0 mm) package outline, 51-85160 package diagrams (continued) 51-85160 *d cy14b101ka cy14b101ma document number: 001-42880 rev. *k page 29 of 34 figure 19. 48-pin ssop (300 mils) package outline, 51-85061 package diagrams (continued) 51-85061 *e cy14b101ka cy14b101ma document number: 001-42880 rev. *k page 30 of 34 acronyms document conventions units of measure acronym description bcd binary coded decimal bhe byte high enable ble byte low enable ce chip enable cmos complementary metal oxide semiconductor eia electronic industries alliance hsb hardware store busy i/o input/output nvsram nonvolatile static random access memory oe output enable rohs restriction of hazardous substances rwi read and write inhibited rtc real time clock sram static random access memory ssop shrink small outline package tsop thin small outline package we write enable symbol unit of measure c degree celsius f farad hz hertz kbit 1024 bits khz kilohertz k ? kilohm mhz megahertz a microampere f microfarad s microsecond ma milliampere ms millisecond ns nanosecond ? ohms % percent pf picofarad ppm parts per million v volt w watt cy14b101ka cy14b101ma document number: 001-42880 rev. *k page 31 of 34 document history page document title: cy14b101ka/cy14b101ma 1-mbit (128 k 8/64 k 16) nvsram with real time clock document number: 001-42880 rev. ecn no. submission date orig. of change description of change ** 2050747 see ecn unc / pyrs new data sheet. *a 2607447 11/18/2008 gvch / aesa removed 15 ns access speed, updated ?features?, added cy14b101ma (x16) part, changed title to ?cy14b101ka/cy14b101ma, 1-mbit (128k x 8/64k x 16) nvsram with real-time-clock?. added 54-pin tsop ii package related information, updated logic block diagram, added footnote 1 and 2. pin definition: updated we , hsb and nc pin description. page 4: updated sram read, sram write, autostore operation description, page 4: updated software store and software recall description updated figure 2, page 4: updated hardware store operation and hardware recall (power up) description footnote 1 and 10 referenced for mode selection table added footnote 10, updated footnote 8 and 9 page 6: updated data protection description page 6: updated starting and stopping the oscillator description page 7: updated calibrating the clock description page 8: added flags register updated table 4, added footnote 12 and 13 updated register map detail table 5 maximum ratings: added max. accumulated storage time changed output short circuit current parameter name to dc output current changed i cc2 from 6 ma to 10 ma changed i cc3 from 15 ma to 35 ma changed i cc4 from 6 ma to 5 ma changed i sb from 3 ma to 5 ma added i ix for hsb updated i cc1, i cc3, i sb and i oz test conditions changed v cap voltage min value from 68uf to 61uf added v cap voltage max value to 180uf updated footnote 14 and 15, added footnote 16 added data retention and endurance table added thermal resistance valu e to 44/54 tsop ii packages updated input rise and fall time in ac test conditions changed v rtccap min value from 1.2 to 1.5v for industrial commercial temperature changed v rtccap min value from 2.7 to 3.6v for industrial commercial temperature updated rtc recommended component configuration values updated tocs value for minimum and room temperature from 10 and 5sec to 2 and 1sec resp. referenced footnote 22 to t oha parameter updated all switching waveforms updated footnote 22, added footnote 25 added figure 11 (sram write cycle:bhe and ble controlled) changed t store max value from 15ms to 8ms updated t delay value added v hdis , t hhhd and t lzhsb parameters updated footnote 29, added footnote 31 and 32 software controlled store/recall table: changed t as to t sa changed t ghax to t ha, changed t ha value from 1ns to 0ns added figure 14 added t dhsb parameter, changed t hlhx to t phsb updated t ss from 70 us to 100 us, added truth table for sram operations updated ordering information a nd part numbering nomenclature cy14b101ka cy14b101ma document number: 001-42880 rev. *k page 32 of 34 *b 2654484 02/05/09 gvch / pyrs changed the data sheet from advance information to preliminary changed x 1 , x 2 pin names to x out , x in respectively updated real time clock operation description added footnotes 11 and 12 added default values to rtc register map? table 3 updated flag register description in register map detail? table 4 changed c1, c2 values to 21pf, 21pf respectively changed i bak value from 350 na to 450 na at hot temperature changed v rtccap typical value from 2.4v to 3.0v referenced note 15 to parameters t lzce , t hzce , t lzoe, t hzoe, t lzbe, t lzwe, t hzwe and t hzbe added footnote 24 updated figure 13 *c 2733909 07/09/09 gvch / aesa page 3; added note to autostore operation description page 4; updated hardware store (hsb ) operation description page 4; updated software store operation description added best practices changed c1, c2 values to 10pf, 67pf respectively changed i bak and v rtccap parameter values added r bkchg parameter updated v hdis parameter description updated t delay parameter description updated footnote 28 and added footnote 35 *d 2757375 08/28/09 gvch moved data sheet status from preliminary to final removed commercial temperature related specs removed 20ns access speed related specs updated thermal resistance values for all the packages changed v rtcbat max value from 3.3v to 3.6v changed r bkchg min value from 450 ?? to 350 ? updated footnote 18 *e 2767333 01/06/10 gvch / pyrs changed store cycles to quantumt rap from 200k to 1 million added data retention and endurance table updated i bak rtc backup current spec unit from na to ? a added contents . *f 2899937 03/26/10 gvch added more clarity on hsb pin operation table 1 : added more clarity on bhe /ble pin opeartion updated hsb pin operation in switching waveforms updated footnote 30 updated ordering information table. updated package diagrams. updated copyright section. *g 3134300 01/11/2011 gvch updated setting the clock description added footnote 15 updated ?w? bit desription in register map detail table updated best practices updated input capacitance for bhe and ble pin updated input and output capacitance for hsb pin added t rtcp parameter to rtc characteristics table figure 12 : typo error fixed added acronyms table and document conventions table *h 3150308 01/21/2011 gvch no technical updates. document history page (continued) document title: cy14b101ka/cy14b101ma 1-mbit (128 k 8/64 k 16) nvsram with real time clock document number: 001-42880 rev. ecn no. submission date orig. of change description of change cy14b101ka cy14b101ma document number: 001-42880 rev. *k page 33 of 34 *i 3313245 07/14/2011 gvch updated dc electrical characteristics (added note 19 and referred the same note in v cap parameter). updated ac switching characteristics (added note 26 and referred the same note in parameters). *j 3500268 01/18/2012 gvch added footnote 8 and 12 . *k 3659138 08/14/2012 gvch updated real time clock operation (description). updated maximum ratings (changed ?ambient temperature with power applied? to ?maximum junction temperature?). updated dc electrical characteristics (added v vcap parameter and its details, added note 21 and referred the same note in v vcap parameter, also referred note 22 in v vcap parameter). updated package diagrams (spec 51-85160 (changed revision from *c to *d)). document history page (continued) document title: cy14b101ka/cy14b101ma 1-mbit (128 k 8/64 k 16) nvsram with real time clock document number: 001-42880 rev. ecn no. submission date orig. of change description of change document number: 001-42880 rev. *k revised august 14, 2012 page 34 of 34 all products and company names mentioned in this document may be the trademarks of their respective holders. cy14b101ka cy14b101ma ? cypress semiconductor corporation, 2008-2012. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 |
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